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Covered reads in the Verilog design files and a VCD or LXT formatted dumpfile from a diagnostic run and generates a database file called a Coverage Description Database (CDD) file, using the score command.
Covereds score command can alternatively be used to generate a CDD file and a Verilog module for using Covered as a VPI module in a testbench which can obtain coverage information in parallel with simulation.
The resulting CDD file can be merged with other CDD files from the same design to create accummulated coverage, using the merge command.
Once a CDD file is created, the user can use Covered to generate various human-readable coverage reports in an ASCII format or use Covereds GUI to interactively look at coverage results, using the report command.
Additionally, as part of Covereds score command, race condition possibilities are found in the design files and can be either flagged as errors, ignoredor flagged as warnings.
By specifying race conditions as errors, Covered can also be used as a race condition checker.
Covered currently supports Verilog-1995, Verilog-2001 (with the exception of config blocks currently), and some SystemVerilog constructs. Metrics that are generated include the following:
- Line coverage
- Toggle coverage
- Memory coverage
- Combinational logic coverage
- FSM state and state-transition coverage
- Assertion (functional) coverage

Enhancements
- This primarily fixes a few bugs in the compile of Covered "out of the box". It
- seems that even with the regression testbench, things can still slip through the cracks.
- Anyhow, please use this release instead of the 0.7.2 release.