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Covered 0.7.3

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Free and open source Verilog code coverage analysis tool Covered reads in the Verilog design files and a VCD or LXT formatted dumpfile from a diagnostic run and generates a database file called a....read more
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Covered 0.7.3 description

Free and open source Verilog code coverage analysis tool Covered reads in the Verilog design files and a VCD or LXT formatted dumpfile from a diagnostic run and generates a database file called a Coverage Description Database (CDD) file, using the...read more

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